Design for test boot camp, part 3: Advanced fault models and cell-aware test

Modern semiconductor testing is based on the notion of a fault model, that is, the expected behavior (response) of a circuit when a defect is present. ATPG (Automatic test pattern generation) tools use fault models to find the patterns required to detect the presence of defects at all points in the circuit. In part 1 of this series we described the most basic fault models and associated tests: the "stuck-at" and "transition" fault models. In this article, we cover a number of more advanced fault models that are commonly used in conjunction with scan testing.